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XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
AC ELECTRICAL CHARACTERISTICS
TA = -40 O TO +85 O C, V CC IS 1.62 TO 3.63V, 70 P F LOAD WHERE APPLICABLE
L IMITS
L IMITS
L IMITS
S YMBOL
P ARAMETER
1.8V ± 10%
2.5V ± 10%
3.3V ± 10%
U NIT
M IN
M AX
M IN
M AX
M IN
M AX
VLIO Data Bus Read/Write Timing
T AS
T AH
T CSL
T LLA
T RD
T LLAR
T LLAW
T DY
T RDV
T DD
T WR
T DS
T DH
Address Setup Time
Address Hold Time
Delay from CS# to LLA#/IOR#/IOW#
LLA# Strobe Width
IOR# Strobe Width
Delay from LLA# to IOR#
Delay from LLA# to IOW#
Read/Write Cycle Delay
Data Access Time
Data Disable Time
IOW# Strobe Width
Data Setup Time
Data Hold Time
15
5
0
10
50
5
5
50
50
15
5
45
25
15
5
0
10
45
5
5
45
45
15
5
40
20
10
5
0
10
40
5
5
40
40
15
5
35
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Modem/Interrupt Timing
T WDO
T MOD
T RSI
T SSI
T RRI
T SI
Delay From IOW# To Output
Delay To Set Interrupt From MODEM Input
Delay To Reset Interrupt From IOR#
Delay From Stop To Set Interrupt
Delay From IOR# To Reset Interrupt
Delay From Start To Interrupt
50
50
50
1
45
45
50
50
50
1
45
45
50
50
50
1
45
45
ns
ns
ns
Bclk
ns
ns
T WTS
T WTS
Delay From Initial IOW# To Transmit Start
(SHR[7:4] = 0x0)
Delay From Initial IOW# To Transmit Start
(SHR[7:4] = 0xF)
8
8
33
48
8
8
33
48
8
8
33
48
Bclk
Bclk
T WRI
T SSR
T RR
T WT
T SRT
T RST
Delay From IOW# To Reset Interrupt
Delay From Stop To Set RXRDY#
Delay From IOR# To Reset RXRDY#
Delay From IOW# To Set TXRDY#
Delay From Center of Start To Reset TXRDY#
Reset Pulse Width
40
45
1
45
45
8
40
45
1
45
45
8
40
45
1
45
45
8
ns
Bclk
ns
ns
Bclk
ns
Bclk
Baud Clock
16X or 8X or 4X of data rate
Hz
53
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